As semiconductor devices scale to smaller dimensions, due to the limits of simple lithography techniques, new approaches have been developed to define devices and features having dimensions that are less than a smallest feature size defined by lithography. Self-aligned multiple patterning (SAMP) schemes have been developed, such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP). These techniques may be used in the semiconductor industry in combination with 193 nm immersion lithography, and potentially in combination with extreme ultraviolet (EUV) lithography. One of the biggest issues for widespread use of SAMP is the significantly higher costs. One manner of reducing costs is to use photoresist instead of other hardmask materials as a first mandrel, which approach in principle eliminates a series of etch and deposition operations. This cost reduction is especially attractive to memory manufacturers whose products are more sensitive to costs.
Notable challenges for using photoresist as a first mandrel include the ability to maintain line edge roughness (LER) and line width roughness below acceptable levels, the need to employ a potentially damaging trim process after lithography, as well as compatibility of photoresist with sidewall material processes used in SAMP schemes. Regarding the latter issue, in a known SAMP process flow, an SiO2 spacer film is deposited directly on a resist-mandrel. In this regard, low-temperature SiO2 deposition processes are employed to avoid resist deformation. The temperature of deposition employed is lower than the photoresist's glass transition temperature, equivalent to a softening temperature, and typically 110° C.-120° C. For example, plasma enhanced atomic layer deposition (PEALD) may be carried out at a temperature of less than ˜80° C. for a duration of less than ˜90 seconds. These low temperature PEALD processes result in reduced conformality, higher reactivity, and enhanced defectivity of the deposited. SiO2 film. This low quality SiO2 spacer exhibits poor etch selectivity, which poor etch behavior places a constraint that a feature formed from this process maintain a minimum height to ensure pattern transfer to a layer below the spacer. The additional operations of critical-dimension (CD) trimming and. LER reduction, employed in a SAMP process flow, place further challenges on maintaining acceptable spacer height requirement, since both CD trimming and LER reduction inherently consume photoresist and result in loss of resist-mandrel height.
Accordingly, with respect to these and other considerations the present disclosure is provided.